1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a dynamic random access memory for performing a refresh operation for recharging stored data.
2. Description of the Related Art
Semiconductor memory devices are largely classified as dynamic random access memories (DRAM) and static random access memories (SRAM). In an SRAM, a unit cell is implemented by four transistors constituting a latching mechanism. Unless the power is interrupted, the stored data is not volatile. Thus, a refresh operation is not necessary. However, in a DRAM, a unit cell is implemented by one transistor and one capacitor, and data is stored in the capacitor. A capacitor formed on a semiconductor substrate is not necessarily completely isolated from peripheral circuits, and therefore, it is possible for the data stored in the memory cell to be altered due to current leakage. Thus, a refresh operation for periodically recharging the data stored in the memory cell is required. A self-refresh operation of a semiconductor memory device is performed while sequentially varying internal addresses by an externally applied command signal.
According to recent trends in highly integrated, large capacitance semiconductor memory devices, a plurality of memory banks are commonly incorporated within a memory chip. Each memory bank is capable of outputting a predetermined amount of data. DRAMs installed on recent systems, including cordless telephones, data banks, Pentium(copyright)-type computer combined personal data assistance (PDA) systems, utilize most memory banks during a data communication mode, while utilizing only specific memory banks for storing data necessary for the system during a standby mode. In order to implement PDA systems, which commonly operate on battery power, it is necessary to minimize power consumption.
FIG. 1 is a block diagram of circuits utilized during a self-refresh operation for a conventional DRAM. In this specification, for the sake of convenience in explanation, a DRAM having four memory banks 101_i (i is an integer from 1 to 4) is illustrated. In FIG. 1, circuit portions related to a self-refresh operation are schematically shown while circuit portions unrelated to the self-refresh operation are not shown.
The respective memory banks 101_i have a plurality of memory cells arranged in columns and rows. Row decoders 103_i define row addresses in the corresponding memory bank. Column decoders 105_1 and 105_2 define column addresses in the corresponding memory bank. A refresh entry detector 107 detects a signal to enter self-refresh operation, and, in response, generates a refresh instruction signal PRFH. In response to a refresh instruction signal PRFH, an internal address generator and counter 109 spontaneously generates sequential addresses FRA1 to FRAn for a self-refresh operation, with the internal addresses being sequentially varied. A switch 111 receives external addresses A1 to An during a normal operating mode and receives the counting addresses FRA1 to FRAn during a refresh mode, and transfers the same to the row decoders 103_i as internal addresses RA1 to RAn.
The self-refresh operation is executed in the following manner. A semiconductor memory device enters into a self-refresh mode in response to an externally input command signal. Then, row addresses are sequentially increased or decreased at predetermined intervals. Word lines of a memory cell are selected sequentially by varying the row addresses. The charge accumulated in the capacitor corresponding to the selected word line is amplified by a sense amplifier and then stored in the capacitor again. Through such a refresh operation, the stored data is retained without loss. This self-refresh operation consumes a large amount of current during the process of sense-amplifying the data stored in the capacitor.
In the conventional DRAM shown in FIG. 1, a self-refresh operation is performed with respect to all memory banks. In other words, even if data is stored in only a specific memory bank, the self-refresh operation is performed on all memory banks.
Furthermore, although separate internal voltage generators 113_i (i is an integer from 1 to 4), including, for example, a back-bias voltage generator or an internal power-supply voltage generator, generally exist for each memory bank, they are all operated during a refresh operation.
As described above, the conventional DRAM performs a self-refresh operation with respect to all memory banks, resulting in unnecessary current dissipation. Also, if a self-refresh mode is entered, all the internal voltage generators existing for each memory bank operate, thereby further increasing current dissipation.
To address the above limitations, it is an object of the present invention to provide a dynamic random access memory (DRAM) having a plurality of memory banks, the DRAM capable of selectively performing a self-refresh operation with respect to individual memory banks.
It is another object of the present invention to provide a DRAM which can reduce power consumption by controlling the operation of an internal voltage generating circuit portion associated with a selective refresh operation for a particular selected memory bank or subset of memory banks.
Accordingly, to achieve the first object, there is provided a dynamic random access memory (DRAM) including a plurality of memory banks capable of being independently accessed, and a refresh controller for selectively performing a refresh operation for one or more memory banks among the plurality of memory banks during a self-refresh operation.
The one or more memory banks may be refreshed according to a combination of control signals.
According to another aspect of the present invention, there is provided a dynamic random access memory (DRAM) including a plurality of memory banks capable of being independently accessed, a plurality of voltage generators disposed to correspond to the respective memory banks, for supplying internal voltages to the memory banks, and a refresh controller for selectively performing a refresh operation for one or more memory banks among the plurality of memory banks during a self-refresh operation, wherein the voltage generators are enabled according to whether or not a refresh operation is performed with respect to the memory banks.
To achieve the second object, there is provided a dynamic random access memory (DRAM) including a plurality of memory banks having a plurality of memory cells arranged in columns and rows, wherein the DRAM is capable of selectively refreshing data stored in each memory bank in a self-refresh mode, the DRAM including a plurality of row decoders for selecting word lines of the memory cells of the memory banks, an address generator for generating internal addresses which sequentially vary during a self-refresh mode, a refresh bank designating circuit for generating refresh bank designating signals for designating a memory bank to be refreshed, and a bank selection decoder for designating one or more memory banks to be refreshed by the refresh bank designating signals and supplying refresh addresses to the row decoders corresponding to the designated memory banks according to the information of the internal addresses.
According to the DRAM of present invention, the self-refresh operation is performed with respect to only a selected memory bank or memory banks in which data is stored, rather than refreshing all memory banks as in the conventional DRAM, thereby minimizing current dissipation. Also, only the internal voltage generator corresponding to the memory bank on which the refresh operation is performed is driven, thereby further reducing current dissipation.